From Sand
to Chip

Every chip begins as sandREFINING — 99.9999999%

The chip's raw material is silicon (Si) — after oxygen, the most abundant element in Earth's crust, making up about 28% of it. It starts out as beach sand (quartz, SiO₂), but to become a semiconductor it must be refined to 'nine-nines (9N)' — 99.9999999% purity.

Melting it with carbon strips away the oxygen, yielding metallurgical-grade silicon of about 98% purity. Running that through the Siemens process — reacting it with hydrogen chloride, distilling, then redepositing it — leaves a chunk of polysilicon with impurities down to one part per billion.

A single-crystal pillar grown while spinningCZOCHRALSKI GROWTH

The polysilicon goes into a quartz crucible and is melted at silicon's melting point of 1,414°C. A finger-sized seed crystal is dipped lightly onto the surface, then slowly pulled upward while rotating — and the molten silicon solidifies following the seed's atomic arrangement exactly, growing into a single-crystal ingot with its atoms in perfect order.

Discovered in 1916 when Polish chemist Jan Czochralski accidentally dipped his pen into molten tin instead of an inkwell, this method is — 110 years later — still the starting point for nearly every wafer.

A canvas sliced out with a diamond sawWAFER SLICING & POLISHING

The ingot is sliced thin with a diamond wire. A disc 300mm across and 0.775mm thick — the wafer.

Grinding down the cut face (lapping), refining it chemically, then polishing it to a mirror finish produces a flawless canvas whose surface undulations are at the nanometer scale. Onto this, hundreds of processes will be stacked.

Cladding silicon in armor of glassOXIDATION

The very first thing done to the mirror-polished wafer is, paradoxically, to cover its surface again. Place the wafer in a high-temperature furnace at 800–1,200°C and flow oxygen or water vapor over it, and a film of silicon dioxide (SiO₂) — glass — grows on the surface.

This oxide film is an insulator that electricity cannot pass through. It is both a protective wall against leakage between circuits and the material for the gate insulator, the heart of the transistor (the electrical switch to be completed at the end of this journey). Its thickness is controlled precisely at the nanometer scale.

Drawing circuits with lightPHOTOLITHOGRAPHY — the heart of chip making

The oxide film grown earlier blankets the whole wafer in one solid layer. Now it is time to draw, with light, the boundary of what to keep and what to carve away. The wafer is coated with light-reactive photoresist, and light is fired through a mask (reticle) engraved with the circuit design, projecting the pattern at one-quarter reduction.

The shorter the wavelength, the finer the line you can draw. So the industry moved from g-line (436nm) → KrF (248nm) → ArF (193nm) all the way to extreme-ultraviolet EUV (13.5nm). EUV light is obtained by hitting flying tin droplets with a laser 50,000 times per second to turn them into plasma; and since it is absorbed by lenses (glass), it is handled only with ultra-precise multilayer mirrors. The company that makes this equipment is, on Earth, ASML alone — a base model running about $200 million each, while the next-generation High-NA EUV that appeared in 2024 reaches about $380 million.

Nanoscale sculptures carved by plasmaETCHING

Using the developed photoresist pattern as a shield, plasma ions carve away only the exposed regions (dry etching). Because the ions strike straight down in anisotropic etching, you can dig deep, narrow trenches that never spread sideways.

In the latest 3D NAND, holes with an aspect ratio over 100:1 — 100 times deeper than they are wide — are punched in a single pass through hundreds of stacked films. It's like drilling straight down 100m into a well just 1m across.

This completes one lap of engraving a single layer of the circuit. Build a layer (oxidation·deposition) → draw with light (photo) → etch it away (etching): this cycle repeats dozens of times, layer after layer — the ①–⑧ you see here is that repetition unrolled into a single line.

Stacking atoms layer by layer, then implantingDEPOSITION & ION IMPLANTATION

Now the reverse — time to build up. With CVD, which reacts gases to lay down a thin film, and ALD, which stacks atoms literally one layer at a time, films just nanometers thick are deposited.

Then an ion implanter accelerates boron (B)·phosphorus (P)·arsenic (As) ions and drives them to a precise depth inside the silicon. Pure silicon barely conducts, but the moment these trace impurities enter, it becomes a true 'semiconductor' whose electricity can be controlled — this is how n-type and p-type are made.

Right after implantation, the ion bombardment has left the silicon's atomic lattice in disarray. A rapid thermal anneal (RTA) immediately flash-heats it to around 1,000°C to repair the lattice and settle the embedded impurities into place — activating them — and only then does current flow.

A 3D highway connecting tens of billionsMETALLIZATION & CMP

Now that the transistors are built, it's time to wire them together. Copper interconnects are stacked 10 or more layers high, and each layer is joined to the next by vertical channels called vias.

Each time a layer is added, CMP (chemical mechanical polishing) grinds the surface flat, and then exposure→etching→deposition repeats on top of it. Because this re-entrant loop runs dozens of times, a single chip takes hundreds of process steps and 2–3 months.

Yield — the number that decides life or deathWAFER TEST & YIELD

A probe card tipped with fine needles touches every die (chip) on the finished wafer and sorts good from bad by electrical signal — this is EDS (Electrical Die Sorting). The share of good dies is the yield — the number that decides whether a foundry business lives or dies.

Most failures come from invisible micro-defects that settle on the wafer during processing. Since defects land randomly per unit area, the larger the die, the more steeply yield falls. Try it for yourself below.

Dressing the chip, and stacking itPACKAGING — THE SECOND MINIATURIZATION

Only the dies screened as good in the earlier test pass into this final gate. The wafer is cut with a blade or laser to separate the dies (dicing), bonded to a substrate, connected to the outside world, and sealed in a protective shell. The connection method has evolved from wire bonding, which joins gold wires, to flip-chip, which flips the die over and connects it directly through bumps.

The latest AI chips take one more leap here — HBM, which stacks DRAM 8–12 layers high and connects them vertically with silicon-piercing electrodes called TSV, all the way to 2.5D packaging (CoWoS), which sets a GPU and HBM side by side on one substrate. This is why packaging is called 'the second miniaturization'.